IBM 0.7nm NanoStack — The Chip That Changes the Axis of Scaling

TL;DR

• IBM unveiled the world's first sub-1nm chip technology — a 0.7nm (7 angstrom) test chip packing nearly 100 billion transistors onto a fingernail-sized die, roughly double the density of its 2021 2nm node.
• The architecture is called NanoStack — a staggered sequential CFET (Complementary FET) design that vertically stacks two layers of nanosheet transistors with independent crystal orientations, solving the signal-routing and power-delivery problems that have plagued 3D transistor stacking.
• Performance claims are extraordinary: 50% higher performance at the same power, or 70% lower power at the same performance, versus IBM's 2nm node. At peak performance, one data point suggests a 79% power reduction.
• SRAM scaling — the silent killer of recent nodes — finally moves: a 40% cell height reduction yielding a projected real-world density of ~55–59 Mb/mm², roughly 50% denser than TSMC N2.
• Five-year path to production. IBM sees smartphone processors and small AI chiplets as the likely first adopters.
• This is not a packaging trick. The gate-merge bonding process operates at the transistor level, not the chiplet level. It is genuine transistor scaling in the z-dimension.

What Happened

On June 25, 2026, IBM Research announced the world's first sub-1-nanometer chip technology from its Yorktown Heights facility. The test vehicle — a 0.7nm node chip — integrates nearly 100 billion transistors on a die roughly the size of a human fingernail (~150 mm²), yielding a transistor density of approximately 666 million transistors per square millimetre ¹.

The architecture, branded NanoStack, is a staggered sequential complementary FET (sCFET) design. Unlike conventional chips where transistors are laid out in a single 2D plane, NanoStack bonds two wafers — one carrying nMOS transistors, the other pMOS — into a vertical stack with the transistors offset from each other. This staggering is not cosmetic: it solves the fundamental signal-routing and power-delivery problem that has made 3D transistor stacking impractical until now.

The announcement was covered by Reuters, BBC, Ars Technica, CNET, Gizmodo, New Scientist, and the semiconductor trade press. The definitive technical analysis comes from Dr. Ian Cutress at More Than Moore, who spent several hours in briefings with IBM's silicon research team ².

What It Actually Means

The axis of scaling has shifted

For five decades, semiconductor progress meant one thing: shrink the transistor in the x-y plane. FinFET (2012) bent the channel upward. Gate-All-Around / nanosheet (2025) wrapped the gate on all four sides. But both were still fundamentally 2D strategies — you were still laying transistors out on a single plane and trying to pack more of them into less area.

NanoStack is different. It doesn't just make transistors smaller — it stacks them. Two complete layers of nanosheet transistors, bonded at the transistor level, with independent optimisation of nMOS and pMOS layers.

This is the difference between building taller skyscrapers and building a second city on top of the first one. The scaling lever is no longer just lithography — it's architecture.

The "0.7nm" label is marketing, and that's fine

Let's be precise about what "0.7nm" means here. As Ars Technica correctly notes, process node names stopped corresponding to physical feature sizes decades ago ³. IBM's 0.7nm node does not have 0.7nm transistor gates — that would be roughly three silicon atoms wide and physically impossible with current materials.

What IBM has done is achieve the effective density of a hypothetical 0.7nm node by stacking two layers of its 2nm-class nanosheet technology. New Scientist reports that IBM declined to give precise component dimensions but the released data "suggests that the technology is essentially two layers of the first working 2-nanometre chip" ⁴.

This is not a criticism. It is how node naming has worked for 20 years. The question is whether the density improvement is real and whether the architecture is manufacturable. On both counts, the answer appears to be yes — with caveats.

The numbers are genuinely staggering

Using the Bohr/Intel density formula, Cutress calculates NanoStack's best-case transistor density at 548 MTr/mm² — more than double TSMC N2's 236 MTr/mm² and Intel 18A's 184 MTr/mm² ². Even the worst-case estimate (~382 MTr/mm²) represents a generational leap.

The SRAM numbers matter even more. SRAM scaling has been the dirty secret of recent process nodes — it barely shrinks, which means the "50% density improvement" on paper translates to far less in real chips that are 30–40% SRAM by area. IBM claims a 40% SRAM cell height reduction, with a theoretical bitcell of 0.011 µm² yielding a projected real-world density of ~55–59 Mb/mm². That is roughly 50% denser than TSMC N2's SRAM and would be the first meaningful SRAM shrink in several generations.

And then there is the power curve. At iso-performance with IBM's 2nm node, NanoStack draws 79% less power at the peak-performance data point. That is not a typo. If it holds in production silicon, it changes the economics of AI inference.

How It Works — The Engineering

The problem with stacking transistors

CFETs — Complementary FETs — have been on the industry roadmap for years. The idea is simple: stack an nMOS transistor on top of a pMOS transistor (or vice versa) to double density without shrinking feature sizes. The problem has always been the same: how do you get power and signal in and out of both layers without the routing becoming a nightmare?

In a conventional aligned CFET, the connections for the top transistor have to snake around the bottom one, forcing narrower sheet widths and adding capacitance. IBM's insight — the staggered design — offsets the two layers so each transistor has direct access to its power and signal lines from opposite sides. Cutress reports that this enables up to a 65% increase in effective gate width per 4-track cell compared to an aligned sCFET ².

The crystal orientation trick

Here is where it gets genuinely clever. nMOS and pMOS transistors perform better with different silicon crystal orientations — nMOS prefers the (001) plane, pMOS prefers (110). In a monolithic design, you are stuck with one orientation and one set of transistors suffers.

IBM's sequential approach uses two different wafers with two different crystal orientations. The pMOS layer is built on a (110) wafer. A second carrier wafer with (001) silicon is bonded on top, the carrier is removed, and the nMOS transistors are built into the new crystal layer. Each transistor type gets its optimal substrate.

The sub-threshold swing — how efficiently the transistor switches — comes in at 68–70 mV/decade. For comparison, FinFETs range from 65–85, planar transistors from 80–100, and GAA is expected to hit 60–75 in its lifetime. For a first-generation research device, this is excellent ².

The secret sauce: gate-merge bonding

IBM is cagey about the exact bonding process, but the outline is clear. A sub-30nm bonding dielectric layer is applied during front-end-of-line processing — before the top transistors are built. This is not a back-end packaging step. It is transistor-level integration.

The bonding layer was verified via scanning acoustic microscopy to be within 1.5nm of uniformity across a full 300mm wafer. IBM claims the bonding oxide contributes only a 2.5% increase in cell-level effective capacitance ².

This is what separates NanoStack from Huawei's recent "logic stacking" claims, which Cutress dismissed as "IP folding" using TSVs — essentially gluing chiplets together and calling it a density improvement. IBM's approach integrates at the cell-library level, not the chip level. It is transistor scaling, not packaging.

Hype Deconstruction

This is a research test vehicle, not a product

IBM does not manufacture chips at volume. The company develops process technology and licenses it to foundries — its primary 2nm licensee is Rapidus in Japan. NanoStack exists as a test chip in a research lab. IBM says it sees a "path to production" in five years. That is realistic for a fundamental transistor architecture change, but it means commercial silicon is unlikely before 2031.

The 666 MTr/mm² number is best-case

That figure comes from dividing 100 billion transistors by a ~150 mm² fingernail-sized die. It is a headline number. The real density in a production chip — with SRAM, I/O, and mixed cell types — will be lower. Cutress's calculated range of 382–548 MTr/mm² using the Bohr formula is more useful for comparison.

Thermal, EDA, and yield are unsolved

IBM acknowledged in briefings that thermal modelling, mechanical stress, power delivery, and EDA tooling all need to be developed in parallel with the process. Designing a chip in 3D at the transistor level requires design tools that understand not just timing and power but also vertical thermal gradients and mechanical strain. IBM says it is working with EDA partners (Synopsys, Cadence) but this is early-stage work.

The five-year timeline could slip

Gate-All-Around took roughly a decade from first research demonstration (IBM's 2017 nanosheet paper) to commercial silicon (Intel 18A in late 2025, TSMC N2 in 2026). CFET is more complex. Five years is ambitious.

Stakeholder Landscape

Cross-Layer Implications

AI hardware economics

The 79% power reduction at iso-performance is the number that should make every AI data centre operator sit up. If NanoStack delivers even half that in production, the cost-per-token for inference drops dramatically. Combined with the SRAM density improvement (more on-chip memory = fewer expensive HBM accesses), this architecture is purpose-built for the AI era.

The Rapidus wildcard

Rapidus — Japan's government-backed attempt to re-enter leading-edge manufacturing — is IBM's primary 2nm licensee and the most likely first manufacturing partner for NanoStack. If Rapidus succeeds in ramping 2nm (target: late 2026 tapeouts, 2027 production) and then licenses NanoStack, Japan becomes a credible third pole in advanced semiconductor manufacturing alongside Taiwan and Korea. The geopolitical implications are significant.

Moore's Law is dead. Long live Moore's Law.

Jensen Huang has been saying Moore's Law is dead for years. IBM's announcement doesn't prove him wrong — it proves that the definition of Moore's Law needs updating. Transistor density doubling every two years through lithography alone is over. Density doubling through architectural innovation — 3D stacking at the transistor level — is just beginning.

As Huiming Bu, IBM's VP of silicon technology research, told Gizmodo: "What we've learned is that progress doesn't stop — it just requires a new paradigm" ⁵.

What This Means for You

If you design AI chips or procure AI infrastructure: NanoStack won't affect your next two generations of silicon. But the architectural direction — vertical integration at the transistor level — is now the confirmed industry trajectory. Your 2030–2032 chip designs should assume CFET-class densities. Start modelling the thermal and power-delivery implications now.

If you work in EDA or chip design tools: The move to 3D transistor-level design is a paradigm shift comparable to the FinFET transition. Tools that understand vertical thermal gradients, mechanical strain, and 3D routing are not optional — they are the next platform. IBM explicitly said it is working with EDA partners. If you are not in those conversations, you are behind.

If you follow AI industry structure: The combination of OpenAI's Jalapeño chip (custom inference silicon) and IBM's NanoStack (next-gen transistor architecture) in the same week is not a coincidence. The AI industry is vertically integrating downward into silicon. The companies that control the transistor control the cost structure. Watch for more AI labs building or licensing custom silicon over the next 18 months.

If you are a general reader: This chip won't be in your phone or laptop until the early 2030s at the earliest. What matters today is that the physical limits everyone worried about — the "end of Moore's Law" — are being pushed back not by making things smaller, but by building them upward. The semiconductor industry just found another gear.

Uncertainty Ledger

Bottom Line

IBM's NanoStack is the most significant transistor architecture announcement since the gate-all-around transition. It doesn't just shrink transistors — it changes the axis of scaling from 2D to 3D at the transistor level. The staggered sequential CFET design, dual crystal orientation, and gate-merge bonding are genuine innovations that solve real problems in vertical transistor integration. The density numbers — 548 MTr/mm² best-case, ~55 Mb/mm² SRAM — represent a generational leap over today's best production nodes. The five-year timeline is ambitious but credible. This is not a product announcement. It is a direction-setting moment. The semiconductor industry just found its next gear, and it runs vertically.

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